1. Field of the Invention
The present invention relates to A/D converters. More particularly, the present invention relates to hybrid A/D converters used in wireless communication systems such as mobile telephones and receiving devices that support multi-mode communication systems.
2. Description of the Related Art
Conventionally, a device provided with a delta-sigma (ΔΣ) modulator that performs differentiation and integration processing on analogue input to send digital output of a low number of bits, such as one bit, is known as an A/D modulator. Normally, digital output of a low number of bits from a delta-sigma modulator is converted to digital output of higher number of bits by a decimation circuit, such as a digital filter.
Receivers in the wireless communication system used in mobile telephones are generally composed of a high-frequency receiver and an A/D converter. The high-frequency receiver selects only the minimal desired waves included in radio waves received at the antenna and lowers the frequency band and amplifies these signals, and outputs baseband analogue signals. This baseband analogue signal is converted into digital signal at the A/D converter and is then input to the demodulation section. The demodulation section carries out error correction, bit synchronization and frame synchronization, and performs demodulation processing.
There is a jumble of wireless communication systems in use worldwide because of various schemes adopted by the primary contractor in accordance with national or local circumstances or strategies. As a result, users must use different wireless terminals that match the communication system provided in their country or region. The existences of multi-mode wireless terminals that support two or more communication systems alleviate inconveniences experienced by users that are active across national boundaries. That also makes it possible for the primary contractor and device manufacturers to support systems worldwide with only one terminal. Therefore, these multi-mode terminals are extremely advantageous because development efficiency has improved and the scope of sales has expanded. Among them, mobile terminals that support both the GSM scheme that has garnered a majority of the world's share, and the W-CDMA scheme that is becoming a next-generation world-wide standard, are considered to be very useful. Along with advancements made to commercialization in recent years, these terminals are expected to become even more compact, to enable longer communication time and less cost.
An A/D converter used as part of a multi-mode mobile terminal receiver will now be explained. To simplify the explanation, an example will be provided of a system that supports both the W-CDMA scheme and GSM scheme (hereinafter referred to as “dual mode”).
The simplest way of implementing a conventional dual-mode A/D converter is to provide separate A/D converters to support both modes. A pipeline-scheme A/D converter is effective for an A/D converter that supports the W-CDMA scheme (for example, see non-patent document 1). A delta-sigma (ΔΣ) modulation-scheme A/D converter is effective for an A/D converter that supports the GSM scheme (for example, see non-patent document 2).
Another way of implementing a dual-mode A/D converter is to use one A/D converter that can switch modes and accommodate both modes separately. Non-patent document 3 presents an example of implementation switching the structure of an A/D converter for the delta-sigma modulation scheme. Also, non-patent documents 4 and 5 show other multi-modes than W-CDMA and GSM. Non-patent documents 4 and 5 provide examples of distinguishing between modes based on the sampling frequency band of a delta-sigma and the effective frequency band after A/D conversion, of a modulation-scheme A/D converter, thus implement a multi-mode A/D converter.    Non-patent Document 1: “A highly Integrated Analog Front-End for 3G” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, No. 5, MAY 2003.    Non-patent Document 2: “A 5 mW ΣΔ Modulator with 84 dB Dynamic Range for GSM/EDGE” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, No. 1, JANUARY 2002.    Non-patent Document 3: “A 1.2-V Dual-Mode WCDMA/GPRS ΔΣ Modulator”, 2003 IEEE International Solid-State Circuits Conference, Session 3, oversampled A/D Converters, 3.3.    Non-patent document 4: “A Tri-Mode Continuous-Time ΣΔ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver” 2003 IEEE International Solid-State Circuits Conference, Session 3, Oversampled A/D Converters, 3.4.    Non-patent document 5: “A Multibit Sigma-Delta ADC for Multimode Receivers” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, No. 3, MARCH 2003.    Non-patent document 6: “DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS” Kluwer Academic Publishers.
Initially, conventional technology will be explained for providing separate A/D converters to support both modes as a dual-mode A/D converter.
FIG. 1 is a block diagram showing a configuration of a conventional pipeline-scheme A/D converter, and shows an example of a pipeline-scheme 8-bit A/D converter generally applied for the W-CDMA scheme. In FIG. 1, the pipeline-scheme 8-bit A/D converter 10 is composed of: pipeline stages 11 provided in six stages; 2-bit A/D converter 12 provided in the final stage; and a digital error correction circuit 13 that adds the digital outputs of pipeline stages 11 and the two-bit A/D converter, to correct errors.
FIG. 2 is a block diagram showing an internal configuration of a pipeline stage 11.
A pipeline stage 11, as shown in FIG. 2, is provided with a 1.5-bit A/D converter 21, 1.5-bit D/A converter 22, analogue adder 23, and two-fold (2×) amplifier 24.
An analogue input signal from the previous stage is A/D converted into 1.5 bits at the 1.5-bit A/D converter 21, and the output of the 1.5-bit A/D converter 21 is used as the digital output signal of the pipeline stage 11. The result of D/A conversion from the output of the 1.5-bit A/D converter 21 is subtracted from the analogue input signal at the analogue adder 23, and the result is amplified by the two-fold amplifier 24 and then transferred onto the next stage.
FIG. 3 shows an example of an analogue circuit for the pipeline stage of a pipeline-scheme A/D converter, and shows a switched-capacitor-type analogue circuit diagram showing an internal structure of the pipeline stage 11. Components that are identical to ones in FIG. 2 use the same reference numerals.
The analogue circuit of the pipeline stage 11 as shown in FIG. 3 is composed of: a 1.5-bit A/D converter 21; analogue switches 31 to 36; two capacitors Cf and Cs; an operational amplifier 37; and a 1.5-bit D/A converter 22 that outputs analogue signals by switching between reference voltages ±VREF and ground voltage (hereinafter 0) according to input.
First, the switch 31 and switch 32 are connected to the input signal side, and the switch 33 is closed. In this state, input signals are applied to the capacitors Cf and Cs. Next, when the switch 33 is opened, the input signal is sampled and saved. Next, the switch 31 is connected to the output of the operational amplifier 37, and the switch 32 is connected to the 1.5-bit D/A converter 22. The 1.5-bit D/A converter 22 selects and applies +VREF, 0 and −VREF voltages, to the capacitor Cs, according to the output of the 1.5-bit A/D converter 21. If Cs =Cf =C, Vout is given by the equation below.    [1]
                              V          out                =                  2          ⁢                      (                                          V                                  i                  ⁢                                                                          ⁢                  n                                            ⁢                              {                                                      +                                          VREF                      2                                                        ,                  0                  ,                                      -                                          VREF                      2                                                                      }                                      )                                              (                  Equation          ⁢                                          ⁢          1                )            
As shown in the equation 1 above, the function of subtracting the D/A conversion result from the input signal and amplifying this two-fold, is implemented.
The chip rate for the W-CDMA scheme is 3.84 Mchips/s, but A/D converters that process baseband analogue signals require sampling at 15.36 MHz, which is four-time oversampling, a bit resolution of 8 bits, and a dynamic range over 44 dB, in the effective frequency band of 1.92 MHz.
The power of the pipeline-scheme A/D converter is mainly consumed by the operational amplifier. The conversion speed is mainly determined by the slew rate and settling of the operational amplifier. For that reason, it is necessary to reduce capacity to lower power consumption, but if 8 bits are required, there is less demand for the accuracy of capacitor matching, and so the capacity can be low. As a result, the requirement for the slew rate and settling is also alleviated, and the load on the operational amplifier is extremely low.
Therefore, with specifications for 15.36 MHz sampling and 8-bit resolution, pipeline-scheme A/D converters are adopted by many manufacturers because of their low power consumption. For the W-CDMA scheme, this is perfect for high-speed, yet comparatively low-resolution A/D converters.
FIG. 4 is a block diagram showing an internal configuration of the delta-sigma modulation-scheme A/D converter. FIG. 4.13 of non-patent document 6 shows an example of a delta-sigma modulation-scheme A/D converter that is generally used for the GSM scheme.
As shown in FIG. 4, the delta-sigma modulation-scheme A/D converter 40 is composed of: three analog integrators 41 to 43; three 4-bit D/A converters 44 to 46; three analogue adders 47 to 49 each positioned at an input section of the analog integrators 41 to 43, that subtract D/A conversion results from the input signal from the previous stage; a quantizer 50 that converts the output of analog integrator 43 of the final stage into digital values; and a dynamic element matching (hereinafter referred to as “DEM”) logic circuit 52 that applies a digital process to whiten or noise-shaping to conversion errors generated at the quantizer 50 and D/A converters 44 to 46. If the analogue input signal is X, and the output of the quantizer 50 is Y, the transmission coefficient in the Z region when the quantized noise generated by the quantizer 50 is Q is shown in equation 2.    [2]Y=X+(1−Z−1)3Q  (Equation 2)
With the input analogue signal X as it is, a noise shaping effect by the (1−Z−1)3 part of the above equation 2 is achieved for the quantization noise Q, which improves low band noise, and, with the effect of oversampling, a high-performance A/D converter is implemented.
FIG. 5 shows a switched capacitor-type analogue circuit that executes operations at each stage of the delta-sigma modulation-scheme A/D converter.
In FIG. 5, the analogue circuit 60 of the delta-sigma modulation-scheme A/D converter is composed of: sixteen sampling capacitors Cs 1 to Cs 16; one integrated capacitor Ci; analogue switches 61 to 71; and an operational amplifier 72. First, the switches 61, 66 and 69, and the switch 62 are turned ON, and the input signals to the sampling capacitors of Cs 1 to Cs 16 are sampled and saved. Next, substantially at the same time these switches are turned OFF, the switch 63 is turned ON, and, at the same time, the switches 64, 67 and 70 or the switches 65, 68 and 71 from the switches 64, 65, 67, 68, 70, and 71 turn ON, and the +VREF or −VREF connected to the ends of the these switches are charged and the electrical charge saved in the sampling capacitors is charged or discharged for subtraction process and integrated to the integral capacitor Ci. In other words, the function for addition (or subtraction), D/A conversion and integration is implemented by this switched capacitor-type analogue circuit 60.
The symbol rate of the GSM scheme is 270.833 k symbols/s. However, to cover the bandwidth of the 8 PSK modulation signal that supports a 2.5th generation GSM standard, called “EDGE,” (for example, see non-patent document 2) that triples the performance of GSMK modulation of the conventional GSM scheme, the A/D converter that processes baseband analogue signals requires a sampling rate of 541.666 kHz, which is twice the symbol rate, an effective frequency band of 180 kHz, and a dynamic range of 84 dB or higher. To convert the above to a bit resolution, it is 14 bits or higher. According to FIG. 2.28 of non-patent document 6, delta-sigma modulation0scheme A/D converter achieves a dynamic range of 90 dB or higher with twenty-four time oversampling or more.
With GSM-scheme mobile telephones, there are many examples where the system clock is 13 MHz. If a delta-sigma modulation-scheme A/D converter is operated at this system clock, approximately thirty-six time oversampling can be ensured for the effective frequency band of 180 kHz, and, by lowering the sampling rate to two-times while removing return images using a decimation digital filter at a later stage, a GSM-scheme A/D converter can be implemented that satisfies the desired specifications.
A pipeline-scheme A/D converter is not suited to a region higher than 12 bits, and so many manufacturers adopt a delta-sigma modulation-scheme A/D converter from the viewpoint of higher performance. These are well suited for A/D converters for GSM that have high resolution and comparatively low-speed.
Conventional technology for using one A/D converter to support both modes as a dual-mode A/D converter, will now be explained.
It has already been explained with reference to FIG. 4 that a delta-sigma modulation-scheme A/D converter is suited for the GSM scheme. According to FIG. 2.28 in non-patent document 6, a dynamic range of 60 dB or higher is possible when this A/D converter is operated at eight-time oversampling. Therefore, a delta-sigma modulation-scheme A/D converter that satisfies the required specifications for W-CDMA can be implemented by operating at 30.72 MHz, which is eight times the double of the effective frequency band of 1.92 MHz, and lowering the sampling rate to four times while removing return images, by a decimation digital filter at a later stage. That is to say, in the GSM mode, the A/D converter is operated at 13 MHz and the sampling rate is lowered to 1/24 with the decimation digital filter at a later stage, and, in the W-CDMA mode, the A/D converter is operated at 30.72 MHz and the sampling rate is lowered the ½ with the decimation digital filter at a later stage. By changing the operation clock and decimation rate according to the mode in use, it is possible to accommodate both modes with a single A/D converter, and there are several examples of application of that principle (see non-patent documents 3, 4, and 5).
Nevertheless, a dual-mode A/D converter that is implemented by providing both the conventional pipeline-scheme A/D converter (FIG. 1) and the delta-sigma modulation-scheme A/D converter (FIG. 4), essentially has the problem of an enlarged circuit surface area, because two A/D converters of substantially the same scale are provided.
Also, the delta-sigma modulation-scheme A/D converter shown in FIG. 4 that supports both modes using one delta-sigma modulation-scheme A/D converter, is operated at a high clock speed of 30.72 MHz in W-CDMA mode, and so the required specifications for the operational amplifier and quantizer, which are the essential analogue circuits, are strict, and, as a result, there is a problem of significant power consumption in W-CDMA mode.